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| DATA SHEET MOS INTEGRATED CIRCUIT PD705100 V830TM 32-BIT MICROCONTROLLER The PD705100 (also called V830) is a microcontroller for incorporation use, which belongs to the V830 familyTM of the NEC original V800 seriesTM microcontrollers. The V830 can achieve high cost-performance for multimedia equipment, by integrating quick real-time responses, high-speed arithmetic/logical instructions, and functions suitable for individual applications. The following user's manual describes details of the functions of the V830. Be sure to read it before designing an application system. V830 User's Manual, Hardware : U10064E V830 User's Manual, Architecture : U12496E FEATURES * High-performance 32-bit architecture for incorporation use * Built-in cache memory Instruction cache : 4K bytes Data cache * Built-in RAM Instruction RAM Data RAM : 4K bytes : 4K bytes : 4K bytes * 16-bit bus fixing function * 16-bit bus system construction * Instructions suitable for variable application * Sum-of-products operation * Saturable operation * Branch prediction * Concatenation shift * Block transfer instructions * One-clock-pitch pipeline structure * 16-/32-bit instructions * Separate buses for addresses and data * 4G-byte linear addresses * Thirty-two 32-bit general-purpose registers * Hardware-interlocked register/flag hazard * 16-level interrupt responses * * Maximum operating frequency Power-saving mode * 100 MHz (internal) * 50/33 MHz (external) * CMOS operation, 3.3-V operation ORDERING INFORMATION Part number Package 144-pin plastic LQFP (fine pitch) (20 x 20 mm) PD705100GJ-100-8EU The information in this document is subject to change without notice. Document No. U11483EJ3V0DS00 (3rd edition) Date Published January 1998 J CP(K) Printed in Japan The mark shows major revised points. (c) 1995, 1996 PD705100 PIN CONFIGURATION 144-pin plastic LQFP (fine pitch) (20 x 20 mm) PD705100GJ-100-8EU GND GND IC1 IC2 RESET IC2 IC2 IC2 GND VDD VDD GND INTV3 INTV2 INTV1 INTV0 INT IC1 GND VDD IC1 ST3 ST2 ST1 ST0 R/W VDD GND A31/CS3 A30/CS2 A29/CS1 A28/CS0 A5 A4 GND GND VDD VDD GND BCLK CMODE IC3 NMI VDD VDD GND A27 A26 A25 A24 A23 A22 GND GND VDD VDD A21 A20 A19 A18 A17 A16 GND VDD A15 A14 A13 A12 A11 A10 VDD VDD 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 VDD A3 A2 A1/BE3 BH/BE2 BE1 BE0 VDD VDD GND BCYST READY HLDRQ HLDAK D0 D16 VDD VDD GND GND D1 D17 D2 D18 D3 D19 GND VDD D4 D20 D5 D21 D6 D22 VDD VDD Caution Leave the IC1 pins open. Connect each IC2 pin to GND via a dedicated resistor. Connect each IC3 pin to VDD via a dedicated resistor. 2 GND GND A9 A8 A7 A6 SIZ16B ASEL GND VDD D31 D15 D30 D14 D29 D13 GND GND VDD VDD D28 D12 D27 D11 D26 D10 VDD GND D25 D9 D24 D8 D23 D7 GND GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 PD705100 PIN NAMES A1-A31 CS0-CS3 D0-D31 BE0-BE3 BH ST0-ST3 BCYST R/W READY HLDRQ HLDAK SIZ16B NMI INT INTV0-INTV3 BCLK CMODE ASEL RESET VDD GND IC1-IC3 : Address Bus : Chip Select : Data Bus : Byte Enable : Byte or Halfword : Status : Bus Cycle Start : Read/Write : Ready : Hold Request : Hold Acknowledge : Bus Size 16 bit : Non-Maskable Interrupt Request : Interrupt Request : Interrupt Level : Bus Clock : Clock Mode : Address Select : Reset : Power Supply : Ground : Internally Connected 3 PD705100 BLOCK DIAGRAM INTV0-INTV3 INT NMI Instruction cache (4K) V830 CPU core Instruction RAM (4K) Barrel shifter Bus interface unit Interrupt controller A1-A31 D0-D31 CS0-CS3 BE0-BE3 BH ST0-ST3 BCYST R/W READY Write buffer (4 stages) SIZ16B HLDRQ General-purpose registers 32 bits x 32 50/33 MHz HLDAK Clock controller ASEL 50/33 MHz Data cache (4K) System registers (11) RESET 32-bit adder (with sum-of-products function) Data RAM (4K) = 100 MHz 4 BCLK CMODE PD705100 CONTENTS 1. PIN FUNCTIONS ........................................................................................................................ 1.1 Pin Functions ................................................................................................................................. 7 7 2. ADDRESS SPACE ..................................................................................................................... 2.1 2.2 Memory Space ................................................................................................................................ I/O Space ......................................................................................................................................... 8 8 10 3. 32-BIT BUS MODE ..................................................................................................................... 3.1 Relationship between External Accesses and Byte Enable Signals ..................................... 13 13 4. 16-BIT BUS MODE ..................................................................................................................... 4.1 16-Bit Bus Sizing ........................................................................................................................... 4.1.1 4.1.2 4.2 Byte/halfword access .................................................................................................... Word access ................................................................................................................... 14 14 14 15 16 Relationship between External Access and Byte Enable Signals ......................................... 5. INTERRUPTS .............................................................................................................................. 5.1 5.2 5.3 Maskable Interrupts ....................................................................................................................... Nonmaskable Interrupts ............................................................................................................... Reset ................................................................................................................................................ 17 17 18 18 6. CLOCK CONTROLLER ............................................................................................................. 6.1 Operation Modes............................................................................................................................ 6.1.1 6.1.2 Sleep mode ..................................................................................................................... Stop mode ....................................................................................................................... 19 19 19 19 7. 8. INTERNAL MEMORY ................................................................................................................. REGISTER SETS ....................................................................................................................... 8.1 Program Register Set .................................................................................................................... 8.1.1 8.1.2 8.2 General-purpose register set ....................................................................................... Program counter (PC) ................................................................................................... 20 21 21 21 22 23 System Register Set ...................................................................................................................... 9. DATA SETS ................................................................................................................................ 9.1 Data Types ...................................................................................................................................... 9.1.1 9.1.2 9.2 Integers ........................................................................................................................... Unsigned integers .......................................................................................................... 24 24 25 25 25 Data Alignment ............................................................................................................................... 10. ADDRESS SPACE ..................................................................................................................... 10.1 Addressing Mode ........................................................................................................................... 10.1.1 10.1.2 Instruction addresses ................................................................................................... Operand addresses ....................................................................................................... 26 27 27 28 5 PD705100 11. INSTRUCTIONS ......................................................................................................................... 11.1 11.2 Instruction Format ......................................................................................................................... Instructions (Listed Alphabetically) ............................................................................................ 29 29 31 12. INTERRUPTS AND EXCEPTIONS ............................................................................................ 13. ELECTRICAL SPECIFICATIONS .............................................................................................. 14. PACKAGE DRAWING ................................................................................................................ 15. RECOMMENDED SOLDERING CONDITIONS ........................................................................ 41 42 61 62 6 PD705100 1. PIN FUNCTIONS 1.1 Pin Functions Pin name A2-A27 A28-A31/CS0-CS3 Note D0-D31 BE0, BE1 Input/output Tristate output Address bus Function At hold Hi-Z Hi-Z/H Hi-Z Hi-Z At reset H H Hi-Z H Address bus/chip select Tristate input/output Tristate output Bidirectional data bus Indicates which data bus can be used for data access. Indicates access to D16-D23/byte or halfword access. Indicates most significant byte access/A1 address. Indicates the status of a bus. Indicates the start of a bus cycle. Indicates whether the bus cycle is a read or write cycle. Input Terminates a bus cycle. Requests bus mastership. Output Input Response to HLDRQ Fixes the bus width to 16 bits. Nonmaskable interrupt request Maskable interrupt request Indicates an interrupt level. Bus clock input Specifies the frequency ratio for the external bus and the internal circuit. Selects A28-A31/CS0-CS3. Resets the internal state. Supplies positive power. Ground potential BE2/BH Hi-Z H BE3/A1 Hi-Z H ST0-ST3 BCYST R/W Hi-Z Hi-Z Hi-Z 0101 H H READY HLDRQ HLDAK SIZ16B NMI INT INTV0-INTV3 BCLK CMODE L - H - ASEL RESET VDD GND - - Note When used for a chip select signal, this is held at the high level. 7 PD705100 2. ADDRESS SPACE 2.1 Memory Space The V830 uses four chip select/address pins and 26 address bus pins to represent a 32-bit address. When the chip select function is used, a 256M-byte image space is created as three spaces and a 32M-byte image space is created as one space. When the chip select function is not used, a 4G-byte linear address space is created. Area 40000000H-7FFFFFFFH in the memory space is reserved as an uncachable area. When this area is accessed, the cache function is not effective. For all other areas, the cache function is effective. Within the memory space, built-in instruction RAM and built-in data RAM are mapped. By accessing these areas, an instruction can be fetched and data loaded/stored within one cycle (internal clock) without activating a bus cycle externally. Data in the built-in instruction RAM, however, cannot be accessed by using the load/store instructions. Nor can instructions be fetched from the built-in data RAM. These built-in RAMs are mapped to the cachable area; however, they are not cached. 8 PD705100 Figure 2-1. Memory Map FFFFFFFFH CS0 Built-in instruction RAM FFFFFFFFH FE001000H FE000FFFH FE000000H Cachable area C0000000H BFFFFFFFH Cachable area 80000000H 7FFFFFFFH CS0 Uncachable area CS3 CS2 40000000H 3FFFFFFFH Cachable area CS3 CS2 CS1 00000000H Built-in data RAM CS1 7FFFFFFFH 7E000000H 6FFFFFFFH 60000000H 5FFFFFFFH 50000000H 4FFFFFFFH 40000000H 2FFFFFFFH 20000000H 1FFFFFFFH 10000000H 0FFFFFFFH 00001000H 00000FFFH 00000000H Chip select signal CS0 Address space 7E000000H-7FFFFFFFH FE001000H-FFFFFFFFH Cachable x CS1 40000000H-4FFFFFFFH 00001000H-0FFFFFFFH x CS2 50000000H-5FFFFFFFH 10000000H-1FFFFFFFH x CS3 60000000H-6FFFFFFFH 20000000H-2FFFFFFFH x 9 PD705100 2.2 I/O Space The V830 represents the I/O space using 32 bits and supports a linear address space of up to 4G bytes. The 1G-byte area C0000000H-FFFFFFFFH is reserved as an internal I/O area. External I/O cannot be placed in this area. When accessing that part of the internal I/O area to which internal I/O is not allocated, normal operation cannot be guaranteed. Figure 2-2. I/O Map FFFFFFFFH Internal I/O area (1G byte) C0000000H BFFFFFFFH External I/O area (1G byte) 80000000H 7FFFFFFFH External I/O area (1G byte) 40000000H 3FFFFFFFH External I/O area (1G byte) 00000000H 10 PD705100 The cache function is not effective within the I/O space. When the chip select function is used, the area is used as the 256M-byte image space represented by A2-A27. Figure 2-3. Image Space Used When Chip Select Function is Used FFFFFFFFH Internal I/O area C0000000H BFFFFFFFH Image 11 Image 10 Image 9 Image 8 80000000H 7FFFFFFFH Image 7 Image 6 Image 5 Image 4 40000000H 3FFFFFFFH Image 3 Image 2 Image 1 Image 0 00000000H 11 PD705100 The upper 1G-byte area (C0000000H-FFFFFFFFH) in the I/O space is reserved for internal I/O. To access internal I/O, the IN.W/OUT.W instructions (in words) must be used. When the internal I/O area is accessed, an external bus cycle is not activated. Figure 2-4. Internal I/O Area FFFFFFFFH Built-in periphery Reserved PLLCR Internal I/O area (1G byte) C0000000H BFFFFFFFH CMCR Reserved IRAMR External I/O area (1G byte) Reserved ICTR 80000000H 7FFFFFFFH Reserved DCTR External I/O area (1G byte) FFFFFFFFH FFFFFFFCH FFFFFFFBH FFFFFFF8H FFFFFFF7H FFFFFFF4H FFFFFFF3H FE001000H FE000FFFH FE000000H FDFFFFFFH FA001000H FA000FFFH FA000000H F9FFFFFFH F2001000H F2000FFFH F2000000H 40000000H 3FFFFFFFH External I/O area (1G byte) 00000000H 12 PD705100 3. 32-BIT BUS MODE If the SIZ16B input, sampled at reset, is inactive, the external bus width becomes 32 bits (32-bit bus mode). In this mode, BE2/BH acts as BE2 and BE3/A1 acts as BE3. 3.1 Relationship between External Accesses and Byte Enable Signals In 32-bit bus mode, BE0-BE3 are output. External accesses are related to byte enable signals as indicated below. Table 3-1. 32-Bit Bus Mode Data length Operand address Bit 1 Bit 0 0 1 0 1 0 0 0 0 0 0 0 BE3 1 1 1 0 1 0 0 0 0 0 0 Byte enable BE2 1 1 0 1 1 0 0 0 0 0 0 BE1 1 0 1 1 0 1 0 0 0 0 0 BE0 0 1 1 1 0 1 0 0 0 0 0 State Byte 0 0 1 1 Ta,Ts Ta,Ts Ta,Ts Ta,Ts Ta,Ts Ta,Ts Ta,Ts Ta,Tb1 Tb2 Tb3 Tb4 Halfword 0 1 Word Burst transfer 0 0 0 0 0 13 PD705100 4. 16-BIT BUS MODE If the SIZ16B input, sampled at reset, is active, the external bus width becomes 16 bits (16-bit bus mode). In this mode, the low-order 16 bits (D0-D15) of the data bus are valid, BE2/BH acts as BH and BE3/A1 acts as A1. The highorder 16 bits (D16-D31) of the data bus enter the high-impedance state. 4.1 16-Bit Bus Sizing The V830 has a bus sizing function by which, to enable access from the data bus to 16 bits of memory or the I/O space, data can be transferred using only the low-order 16 bits of the 32-bit data bus. When the SIZ16B input is activated upon a reset, the external data bus width becomes 16 bits (16-bit bus mode). In 16-bit bus mode, D16-D31 are all set to the high-impedance state and BE0, BE1, BH, and A1 are output in a way suited to a 16-bit bus system. Connection to D16-D31 is not necessary. The SIZ16B input can be changed only when the V830 is reset. It cannot be changed at any other time. 4.1.1 Byte/halfword access Bus cycles in either of two bus states (Ta and Ts) are used for byte/halfword access. (1) Upper halfword During read cycles, data is read from D0-D15. During write cycles, D16-D31 data read from the write buffer is output to D0-D15. Figure 4-1 illustrates the operation for upper halfword access. In this figure, B indicates the upper halfword (highorder 16 bits of the word). Figure 4-1. Upper Halfword Access Read cycle Read buffer 31 31 B Internal operation unit 16 15 16 15 B 0 0 Data bus Write cycle Write buffer 31 31 B Internal operation unit 16 15 16 15 B 0 0 Data bus 14 PD705100 (2) Lower halfword During read cycles, data is read from D0-D15. During write cycles, D0-D15 data read from the write buffer is output to D0-D15. Figure 4-2 shows the operation for lower halfword access. In this figure, A indicates the lower halfword (low-order 16 bits of the word). Figure 4-2. Lower Halfword Access Read cycle Read buffer 31 31 Internal operation unit Data bus Write cycle Write buffer 31 31 Internal operation unit A 0 0 Data bus 16 15 A 0 16 15 16 15 A 16 15 A 0 4.1.2 Word access Bus cycles in any of three bus states (Ta, Tw1, and Tw2) are used for word access. During a read cycle, the low-order 16 bits of data and high-order 16 bits of data are sampled from D0-D15 in the Tw1 and Tw2 state, respectively. During write cycles, the low-order 16 bits of data and high-order 16 bits of data are output to D0-D15 in the Ta/Tw1 state and Tw2 states, respectively. Figure 4-3. Read Cycle Tw1 state Read buffer 31 31 Internal operation unit Data bus Tw2 state Read buffer 31 B Internal operation unit A 0 0 31 Data bus 16 15 A 0 16 15 16 15 A 16 15 B 0 15 PD705100 Figure 4-4. Write Cycle Ta, Tw1 state Write buffer 31 31 B Internal operation unit 16 15 A 0 0 16 15 A Data bus Tw2 state Write buffer 31 31 Internal operation unit B 16 15 16 15 B 0 0 Data bus 4.2 Relationship between External Access and Byte Enable Signals In 16-bit bus mode, the BE3/A1 output acts as A1 and BE2/BH output acts as BH. External accesses are related to the byte enable signals as indicated below. Table 4-1. 16-Bit Bus Mode Data length Operand address Bit 1 Bit 0 0 1 0 1 0 0 0 A1 0 0 1 1 0 1 0 1 Byte enable BH 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 BE1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 BE0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 State Byte 0 0 1 1 Ta,Ts Ta,Ts Ta,Ts Ta,Ts Ta,Ts Ta,Ts Ta,Tw1 Tw2 Ta,Tb1 Tb2 Tb3 Tb4 Tb5 Tb6 Tb7 Tb8 Halfword 0 1 Word 0 Burst transfer 0 0 0 1 0 1 0 1 0 1 16 PD705100 5. INTERRUPTS V830 interrupts include maskable interrupts, nonmaskable interrupts, and reset operations. 5.1 Maskable Interrupts Maskable interrupt requests are themselves denoted by INT, and their interrupt levels by INTV0 to INTV3. The following lists pin states and the corresponding interrupt levels. Table 5-1. Interrupt Levels Interrupt level 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 INTV3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 INTV2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 INTV1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 INTV0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 INT and INTV0 to INTV3 are level inputs. The V830 samples an INT at the rising edge of a bus clock pulse. INT and INTV0 to INTV3 should be held at the active level until the V830 accepts the interrupt request and posts to a peripheral, by software, notification of the acceptance of the interrupt request. Although a change to a higher interrupt level is possible, the timing at which an interrupt request is detected cannot then be posted to peripheral. Hence, an interrupt request made before such a change may be accepted. If the interrupt request input (INT, INTV0INTV3) fails to satisfy the setup time requirement for the bus clock pulse, the interrupt request will be detected at the rising edge of the next bus clock pulse. Upon accepting an interrupt request, the V830 jumps to a fixed address to start interrupt handling. The target address of the jump is set to FE0000n0H (built-in RAM) or FFFFFEn0H (external memory), where n is the interrupt level, either of which may be specified with the IHA bit of the system register, HCCW. Caution Interrupt level 15 is reserved for use by development tools (in-circuit emulator, ROM emulator, etc). If the user uses interrupt level 15, those development tools may fail to operate. 17 PD705100 5.2 Nonmaskable Interrupts The V830 samples an NMI at the rising edge of a bus clock pulse. When the NMI changes from the high to low level, an interrupt request is detected. Once a nonmaskable interrupt request has been detected, the NMI can subsequently be deactivated at any time because the NMI is detected at the falling edge. An interrupt request thus detected is retained in the CPU until the CPU starts interrupt handling. Upon accepting a nonmaskable interrupt, the V830 jumps to the fixed address (FFFFFFD0H). If another nonmaskable interrupt is issued during nonmaskable interrupt handling (the NP bit of PSW is set to1), it is retained in the processor. If, however, another nonmaskable interrupt request is issued during clearing of the latch circuit by internal processing after the start of nonmaskable interrupt handling, it is not retained in the processor. 5.3 Reset The V830 can be reset by inputting a low-level signal of 20 or more clock pulses to RESET. After the V830 has been reset, the CPU starts program execution from address FFFFFFF0H. If RESET is driven high, the CPU starts instruction fetching from the reset address. Immediately after power-on or in the stop-mode state, the active pulse width of the RESET should be determined by adding the PLL oscillation settling time to the active level of 20 clock pulses. 18 PD705100 6. CLOCK CONTROLLER 6.1 Operation Modes The V830 supports two clock stop functions, namely, sleep mode and stop mode. Transition from one mode to another is made by executing special instructions HALT or STBY. The following lists the features of these modes: Table 6-1. Operation Modes Sleep mode V830 Internal state Internal clock stop PLL operation continuous Bus hold acceptable Built-in RAM/cache data hold Entry to mode Escape from mode HALT instruction Maskable interrupt/NMI/reset Stop mode Internal clock stop PLL operation stop Bus hold unacceptable Built-in RAM/cache data hold STBY instruction NMI/reset 6.1.1 Sleep mode The V830 enters sleep mode upon the execution of a HALT instruction. On the other hand, escape from sleep mode can be realized by a maskable interrupt, NMI, or reset operation. In sleep mode, bus hold requests can be accepted. During bus hold, the status becomes high impedance and no halt acknowledge status is output. At the end of bus hold, a halt acknowledge status is output in sync with the rising edge of a bus clock pulse. 6.1.2 Stop mode The V830 enters stop mode when an STBY instruction is executed. On the other hand, escape from stop mode can be realized using an NMI or a reset operation. The power consumption in stop mode is less than that in the sleep mode because the PLL circuit stops. Also, no bus hold requests are accepted in the stop mode. 19 PD705100 7. INTERNAL MEMORY The V830 has a 4K bytes x 4 internal memory, consisting of four blocks (instruction cache, data cache, instruction RAM, and data RAM). The V830 allows any of these internal memory blocks to be accessed in one cycle. Figure 7-1. Built-In Cache Configuration Instruction bus V830 CPU core Instruction cache Decoder Instruction RAM External memory Execution unit Data cache Data RAM Data bus Cautions 1. Data can not be written into the instruction cache or instruction RAM. 2. A instruction can not be written into the data cache or data RAM. 20 PD705100 8. REGISTER SETS 8.1 Program Register Set The V830 has two types of register sets: general-purpose register sets which can be used by programmers, and system register sets which control the state of the V830. The width of all registers is 32 bits. 8.1.1 General-purpose register set (1) General-purpose registers The V830 has 32 general-purpose registers, r0-r31, which can be used either as data registers or address registers. Note, however, that r0, r30, and r31 contain values that are fixed by hardware or which are used implicitly by instructions. (a) Hardware-dependent registers Hardware-dependent registers contain values that are fixed by hardware or which are used implicitly by instructions. r0 : Zero register Always contains 0. r30 : Register reserved for operation Serves as an auxiliary register which stores the result of a multiplication or division instruction. r31 : Link pointer The JAL instruction stores the return address in this register. (b) Software-reserved registers These registers are used by assemblers and compilers. To use them as registers for variables, first save their contents to guard against data loss or damage. When their use is no longer required restore the saved contents. r1 : Assembler-reserved register Serves as a working register for creating 32 bits of immediate data. It is used implicitly when the assembler calculates an effective address. r2 r3 r4 r5 : Handler stack pointer Reserved as the stack pointer for a handler. : Stack pointer Reserved for stack frame creation when a function is called. : Global pointer Used when accessing a global variable in a data area. : Text pointer Points to the beginning of a text area. 21 PD705100 8.1.2 Program counter (PC) The program counter (PC) is a register which holds the first address of the instruction being executed. Bit 0 of the program counter is fixed to 0, but is forcibly masked to 0 upon a branch to a point other than a halfword boundary (bit 0 of the address is 0). Upon reset, the program counter is initialized to FFFFFFF0H. Figure 8-1. Program Registers r0 : Zero register r1 : Assembler-reserved register r2 : Handler stack pointer r3 : Stack pointer r4 : Global pointer r5 : Text pointer r6 r29 r30: Register reserved for operation r31: Link pointer PC 22 PD705100 8.2 System Register Set System registers are used to control the processor state, save exception/interruption information, and manage tasks. The V830 has eleven 32-bit system registers. These registers can be accessed using special instructions (LDSR and STSR instructions). Figure 8-2. System Registers #0 #1 #2 #3 #4 #5 EIPC EIPSW FEPC FEPSW ECR PSW #6 #7 #16 #17 #31 PIR TKCW DPC DPSW HCCW Remark The system register number is preceded by #. 23 PD705100 9. DATA SETS 9.1 Data Types The V830 supports three data types: byte (8 bits), halfword (16 bits), and word (32 bits). Data of these types must be aligned with byte, halfword, or word boundaries, respectively. Addressing is based on little endian. (1) Byte data One byte of data consists of eight consecutive bits, each of which is named. Bit 0 is the LSB (Least Significant Bit) while bit 7 is the MSB (Most Significant Bit). This data can be placed at any address. 7 MSB Address 0 LSB A (2) Halfword data One halfword of data consists of 16 consecutive bits, each of which is named. Bit 0 is the LSB, while bit 15 is the MSB. Halfword data must be aligned with halfword boundaries (in address areas such that bit 0 of the address of the segment containing bit 0 is 0). 15 87 A+1 0 Address A A = 2n (where n is a positive integer) (3) Word data One word of data consists of 32 consecutive bits, each of which is named. Bit 0 is the LSB and bit 31 is the MSB. Word data must be aligned with word boundaries (in address areas such that bits 0 and 1 of the address of the segment containing bit 0 are 0). 31 16 15 0 Address A+3 A+2 A+1 A A = 4n (where n is a positive integer) 24 PD705100 9.1.1 Integers In the V830, integers are represented by twos complements. They are expressed by bytes, halfwords, or words. Digit ordering for integers is as follows: Bit 0 is handled as the least significant bit, regardless of the data length. Larger bit numbers correspond to higher orders. Data length Byte (8 bits) Halfword (16 bits) Word (32 bits) Range (in decimal notation) -128 to +127 -32 768 to +32 767 -2 147 483 648 to +2 147 483 647 9.1.2 Unsigned integers Unsigned integers are of a data type for which the most significant bit is not handled as a sign bit, but all bits represent a positive integer. Data of this data type is represented by a binary number and has a size of a byte, halfword, or word. Digit ordering for unsigned integers is as follows: Bit 0 is handled as the least significant bit, regardless of the data length. Larger bit numbers correspond to higher orders. Data length Byte (8 bits) Halfword (16 bits) Word (32 bits) Range (in decimal notation) 0 to 255 0 to 65 535 0 to 4 294 967 295 9.2 Data Alignment The V830 requires that data be aligned with appropriate boundaries: word boundaries for word data, halfword boundaries for halfword data, and byte boundaries for byte data. If a data alignment error is detected, the data address is automatically changed to an accessible address. It is impossible to predict whether this address change will lead to correct or incorrect data access. This change is made as follows: Data size Byte data Halfword data Word data -- Method Bit 0 is masked to 0. Bits 0 and 1 are masked to 0. 25 PD705100 10. ADDRESS SPACE The V830 supports 4G-byte linear address spaces for both the memory space and I/O space. It assigns 32-bit addresses to the memory space. The maximum address is 232 - 1. It also assigns 32-bit addresses to the I/O space. Byte data aligned with each address is defined such that bits 0 and 7 are the LSB and MSB, respectively. If data consists of multiple bytes, it is defined such that the byte data at the low-order address contains the LSB and that at the high-order address contains the MSB (little-endian ordering), unless specified otherwise. According to V830 terminology, data arranged in two-byte format is called halfword data, while that arranged in four-byte format is called word data. For data consisting of multiple bytes, the low-order address on the right and the high-order address on the left, as indicated below. 7 Byte at address A A 15 Halfword at address A A+1 31 Word at address A A+3 A+2 A+1 A 24 23 16 15 8 7 A 0 Data Address 8 7 0 Data Address 0 Data Address 26 PD705100 10.1 Addressing Mode The V830 generates two types of addresses, as follows: * Instruction addresses (used by instructions involving branching) * Operand addresses (used by instructions which access data) 10.1.1 Instruction addresses The instruction address is determined by the contents of the program counter (PC). Each time an instruction is executed, it is automatically incremented by 2 or 4, depending on the number of bytes constituting the instruction being fetched. When a branch instruction is executed, the branch address is set in the PC by the following addressing mode: (1) Relative addressing (to PC) The signed 9 or 26 bits (displacement, or disp) of data contained in the operation code are added to the program counter (PC). For this addition, the displacement is handled as twos complement data. Bit 8 or 25 is the sign bit, respectively. The JR, JAL, Bcond, and ABcond instructions use this addressing. Addressing for JR and JAL instructions 31 PC 31 26 25 S + disp 26 0 0 0 0 0 PC 0 Sign extension 31 Addressing for Bcond and ABcond instructions 31 PC 31 Sign extension 31 PC + 98 S disp 9 0 0 0 0 0 0 27 PD705100 (2) Register addressing (via register) The contents of the general-purpose register (r0-r31) designated in the instruction are transferred to the program counter (PC). The JMP instruction uses this addressing. 31 Register m 31 PC 0 0 0 10.1.2 Operand addresses (1) Register addressing In this addressing mode, the general-purpose register designated in the general-purpose register designation field is accessed as an operand. This addressing is used by instructions whose operand format is reg1 or reg2. (2) Immediate addressing In this addressing mode, the 5 or 16 bits of data constituting the operation code are handled as an operand. This addressing is used by those instructions whose operand format is imm5 or imm16. (3) Based addressing In this addressing mode, when the memory area containing the operand is accessed, its address is determined from the sum of the contents of the general-purpose register designated by the address designation code and the 16-bit displacement in the instruction. This addressing is used by those instructions having an operand format of disp16[reg1]. 31 reg 1 31 Sign extension 16 15 disp 16 0 0 28 PD705100 11. INSTRUCTIONS 11.1 Instruction Format The V830 uses two instruction formats: 16-bit and 32-bit. The 16-bit instructions include binary operation, control, and conditional branch instructions, while the 32-bit instructions include load/store and I/O operation instructions, instructions for handling 16 bits of immediate data, and jump-and-link instructions. Some instructions contain unused fields, which must be fixed to 0, which are provided for future use. When an instruction is actually loaded into memory, its configuration is as follows: * Low-order part of each instruction format (including bit 0) Low-order address * High-order part of each instruction format (including bit 15 or 31) High-order address (1) reg-reg instruction format [FORMAT I] This instruction format has a six-bit operation code field and two general-purpose register designation fields for operand specification, giving a total length of 16 bits. 15 opcode 10 9 reg 2 54 reg 1 0 (2) imm-reg instruction format [FORMAT II] This instruction format has a six-bit operation code field, a five-bit immediate data field, and a general-purpose register designation field, giving a total length of 16 bits. 15 opcode 10 9 reg 2 54 imm 5 0 (3) Conditional branch instruction format [FORMAT III] This instruction format has a three-bit operation code field, a four-bit condition code field, a nine-bit branch displacement field (bit 0 is handled as 0 and need not be specified), and a one-bit sub-operation code, giving a total length of 16 bits. 15 98 cond disp 9 10 s s = 0 : Bcond s = 1 : ABcond 13 12 opcode s : sub-opcode 29 PD705100 (4) Medium-distance jump instruction format [FORMAT IV] This instruction format has a six-bit operation code field and a 26-bit displacement field (the lowest-order bit must be 0), giving a total length of 32 bits. 15 opcode 10 9 0 31 disp 26 16 0 (5) Three-operand instruction format [FORMAT V] This instruction format has a six-bit operation code field, two general-purpose register designation fields, and a 16-bit immediate data field, giving a total length of 32 bits. 15 opcode 10 9 reg 2 54 reg 1 0 31 imm 16 16 (6) Load/store instruction format [FORMAT VI] This instruction format has a six-bit operation code field, two general-purpose register designation fields, and a 16-bit displacement field, giving a total length of 32 bits. 15 opcode 10 9 reg 2 54 reg 1 0 31 disp 16 16 (7) Extended instruction format [FORMAT VII] This instruction format has a six-bit operation code field, two general-purpose register designation fields, and a six-bit sub-operation code field, giving a total length of 32 bits. 15 opcode 10 9 reg 2 54 reg 1 0 31 sub-opcode 26 25 RFU 16 (8) Three-register operand instruction format [FORMAT VIII] This instruction format has a six-bit operation code field, three general-purpose register designation fields, and a six-bit sub-operation code field, giving a total length of 32 bits. 15 opcode 10 9 reg 2 54 reg 1 0 31 sub-opcode 26 25 RFU 21 20 reg 3 16 (9) No-operand instruction format [FORMAT IX] This instruction format has a six-bit operation code field and a one-bit sub-operation code field, giving a total length of 16 bits. 15 opcode s : sub-opcode 10 9 RFU 10 s 30 PD705100 11.2 Instructions (Listed Alphabetically) The instructions are listed below in alphabetic order of their mnemonics. Explanation of list format Instruction ADD Operand(s) reg1, reg2 Format CY OV I * * S * Z * Function Instruction mnemonic Instruction format (See Section 11.1.) Indicates how each flag changes. - : Does not change. * : Changes. 0 : Becomes 0. 1 : Becomes 1. Abbreviations of operands Abbreviation reg1 reg2 Meaning General-purpose register (used as a source register) General-purpose register (used mainly as a destination register, but in some instructions, used as a source register) General-purpose register (used mainly as a destination register, but in some instructions, used as a source register) x bits of immediate data x-bit displacement System register number Trap handler address corresponding to trap vector reg3 immx dispx regID vector adr 31 PD705100 Instruction ABC Operand(s) disp9 Format III CY OV S Z Function High-speed conditional branch (if Carry) relative to PC. High-speed conditional branch (if Equal) relative to PC. High-speed conditional branch (if Greater than or Equal) relative to PC. High-speed conditional branch (if Greater than) relative to PC. High-speed conditional branch (if Higher) relative to PC. High-speed conditional branch (if Lower) relative to PC. High-speed conditional branch (if Less than or Equal) relative to PC. High-speed conditional branch (if Less than) relative to PC. High-speed conditional branch (if Negative) relative to PC. High-speed conditional branch (if Not Carry) relative to PC. High-speed conditional branch (if Not Equal) relative to PC. High-speed conditional branch (if Not Higher) relative to PC. High-speed conditional branch (if Not Lower) relative to PC. High-speed conditional branch (if Not Overflow) relative to PC. High-speed conditional branch (if Not Zero) relative to PC. High-speed conditional branch (if Positive) relative to PC. High-speed unconditional branch (Always) relative to PC. High-speed conditional branch (if Overflow) relative to PC. High-speed conditional branch (if Zero) relative to PC. Addition. reg1 is added to reg2 and the sum is written into reg2. Addition. imm5, sign-extended to a word, is added to reg2 and the sum is written into reg2. Addition. imm16, sign-extended to a word, is added to reg1, and the sum is written into reg2. ABE disp9 III - - - - ABGE disp9 III - - - - ABGT disp9 III - - - - ABH disp9 III - - - - ABL disp9 III - - - - ABLE disp9 III - - - - ABLT disp9 III - - - - ABN disp9 III - - - - ABNC disp9 III - - - - ABNE disp9 III - - - - ABNH disp9 III - - - - ABNL disp9 III - - - - ABNV disp9 III - - - - ABNZ disp9 III - - - - ABP disp9 III - - - - ABR disp9 III - - - - ABV disp9 III - - - - ABZ disp9 III ADD reg1, reg2 I imm5, reg2 II ADDI imm16, reg1, reg2 V 32 PD705100 Instruction AND Operand(s) reg1, reg2 Format I CY OV 0 S Z Function AND. reg2 and reg1 are ANDed and the result is written into reg2. AND. reg1 is ANDed with imm16, zero-extended to a word, and result is written into reg2. Conditional branch (if Carry) relative to PC. Block transfer. 4 words of data are transferred from external memory to built-in data RAM. Block transfer. 4 words of data are transferred from built-in data RAM to external memory. Conditional branch (if Equal) relative to PC. Conditional branch (if Greater than or Equal) relative to PC. Conditional branch (if Greater than) relative to PC. Conditional branch (if Higher) relative to PC. Block transfer. 4 words of data are transferred from external memory to built-in instruction RAM. Block transfer. 4 words of data are transferred from built-in instruction RAM to external memory. Conditional branch (if Lower) relative to PC. Conditional branch (if Less than or Equal) relative to PC. Conditional branch (if Less than) relative to PC. Conditional branch (if Negative) relative to PC. Conditional branch (if Not Carry) relative to PC. Conditional branch (if Not Equal) relative to PC. Conditional branch (if Not Higher) relative to PC. Conditional branch (if Not Lower) relative to PC. Conditional branch (if Not Overflow) relative to PC. Conditional branch (if Not Zero) relative to PC. Conditional branch (if Positive) relative to PC. Unconditional branch (Always) relative to PC. Return from fatal exception handling. Conditional branch (if Overflow) relative to PC. Conditional branch (if Zero) relative to PC. Inter-processor synchronization in multiprocessor system. ANDI imm16, reg1, reg2 V - 0 0 BC BDLD disp9 [reg1], [reg2] III VII - - - - BDST [reg2], [reg1] VII - - - - BE BGE disp9 disp9 III III - - - - BGT disp9 III - - - - BH BILD disp9 [reg1], [reg2] III VII - - - - BIST [reg2], [reg1] VII - - - - BL BLE disp9 disp9 III III - - - - BLT BN BNC BNE BNH BNL BNV disp9 disp9 disp9 disp9 disp9 disp9 disp9 III III III III III III III - - - - BNZ BP BR BRKRET BV BZ CAXI disp9 disp9 disp9 III III III IX disp9 disp9 disp16[reg1], reg2 III III VI 33 PD705100 Instruction CMP Operand(s) reg1, reg2 I Format CY OV S Z Function Comparison. reg2 is compared with reg1 sign-extended to a word and the condition flag is set according to the result. The comparison involves subtracting reg1 from reg2. Comparison. reg2 is compared with imm5 sign-extended to a word and the condition flag is set according to the result. The comparison involves subtracting imm5, sign-extended to a word, from reg2. Disable interrupt. Maskable interrupts are disabled. DI instruction cannot disable nonmaskable interrupts. Division of signed operands. reg2 is divided by reg1 (signed operands). The quotient is stored in reg2 and the remainder in r30. The division is performed so that the sign of the remainder will match that of the dividend. DIVU reg1, reg2 I 0 Division of unsigned operands. reg2 is divided by reg1 (unsigned operands). The quotient is stored in reg2 and the remainder in r30. The division is performed so that the sign of the remainder will match that of the dividend. Enable interrupt. Maskable interrupts are enabled. The EI instruction cannot enable nonmaskable interrupts. Processor halt. The processor is placed in sleep mode. Port input. disp16, sign-extended to a word, is added to reg1 to produce an unsigned 32-bit port address. A byte of data is read from the resulting port address, zero-extended to a word, then stored in reg2. Port input. disp16, sign-extended to a word, is added to reg1 to produce an unsigned 32-bit port address. A halfword of data is read from the produced port address, zero-extended to a word, and stored in reg2. Bit 0 of the unsigned 32-bit port address is masked to 0. Port input. disp16, sign-extended to a word, is added to reg1 to produce an unsigned 32-bit port address. A word of data is read from the resulting port address, then written into reg2. Bits 0 and 1 of the unsigned 32-bit port address are masked to 0. imm5, rag2 II DI II - - - - DIV reg1, reg2 I - EI II - - - - HALT IX - - - - IN.B disp16[reg1], reg2 VI - - - - IN.H disp16[reg1], reg2 VI - - - - IN.W disp16[reg1], reg2 VI - - - - 34 PD705100 Instruction JAL Operand(s) disp26 Format IV CY OV S Z Function Jump and link. The sum of the current PC and 4 is written into r31. disp26, sign-extended to a word, is added to the PC and the sum is set to the PC for control transfer. Bit 0 of disp26 is masked. Indirect unconditional branch via register. Control is passed to the address designated by reg1. Bit 0 of the address is masked to 0. Unconditional branch. disp26, sign-extended to a word, is added to the current PC and control is passed to the address specified by that sum. Bit 0 of disp26 is masked to 0. Byte load. disp16, sign-extended to a word, is added to reg1 to produce an unsigned 32-bit address. A byte of data is read from the produced address, sign-extended to a word, then written into reg2. LD.H disp16[reg1], reg2 VI Halfword load. disp16, sign-extended to a word, is added to reg1 to produce an unsigned 32-bit address. A halfword of data is read from the produced address, sign-extended to a word, then written into reg2. Bit 0 of the unsigned 32-bit address is masked to 0. Word load. disp16, sign-extended to a word, is added to reg1 to produce an unsigned 32-bit address. A word of data is read from the produced address, then written into reg2. Bits 0 and 1 of the unsigned 32-bit address are masked to 0. Load into system register. The contents of reg2 are set in the system register identified by the system register number (regID). Saturatable operation on signed 32-bit operands. reg1 and reg2 are multiplied together as signed integers and the product is added to reg3. [If no overflow has occurred:] The result is stored in reg3. [If an overflow has occurred:] The SAT bit is set. If the result is positive, the positive maximum is written into reg3; if the result is negative, the negative maximum is written into reg3. JMP [reg1] I - - - - JR disp26 IV - - - - LD.B disp16[reg1], reg2 VI - - - - LD.W disp16[reg1], reg2 VI - - - - LDSR reg2, regID II MAC3 reg1, reg2, reg3 VIII - - - - 35 PD705100 Instruction MACI Operand(s) imm16, reg1, reg2 Format V CY OV S Z Function Sum-of-products operation on signed 32-bit operands. reg1 and imm16, sign-extended to 32 bits, are multiplied together as signed integers and the product is added to reg2 as a signed integer. [If no overflow has occurred:] The result is written into reg2. [If an overflow has occurred:] The SAT bit is set. If the result is positive, the positive maximum is written into reg2; if the result is negative, the negative maximum is written into reg2. MACT3 reg1, reg2, reg3 VIII Saturatable operation on signed 32-bit operands. reg1 and reg2 are multiplied together as signed integers and the high-order 32 bits of the product are added to reg3 as signed integers. [If no overflow has occurred:] The result is written into reg3. [If an overflow has occurred:] The SAT bit is set. If the result is positive, the positive maximum is written into reg3; if the result is negative, the negative maximum is written into reg3. MAX3 reg1, reg2, reg3 VIII Maximum. reg2 and reg1 are compared as signed integers. The larger value is written into reg3. Minimum. reg2 and reg1 are compared as signed integers. The smaller value is written into reg3. Data transfer. reg1 is copied to reg2 for data transfer. Data transfer. imm5, sign-extended to a word, is copied into reg2 for data transfer. MOVEA imm16, reg1, reg2 V Addition. The high-order 16 bits (imm16), sign-extended to a word, are added to reg1 and the sum is written into reg2. Addition. A word consisting of the high-order 16 bits (imm16) and low-order 16 bits (0) is added to reg1 and the sum is written into reg2. Multiplication of signed operands. reg2 and reg1 are multiplied together as signed values. The high-order 32 bits of the product (double word) are written into r30 and low-order 32 bits are written into reg2. Multiplication of signed 32-bit operands. reg2 and reg1 are multiplied together as signed integers. The high-order 32 bits of the product are written into reg3. MIN3 reg1, reg2, reg3 VIII - - - - MOV reg1, reg2, I - - - - imm5, reg2 II - - - - MOVHI imm16, reg1, reg2 V - - - - MUL reg1, reg2 I - MUL3 reg1, reg2, reg3 VIII - - - - 36 PD705100 Instruction MULI Operand(s) imm16, reg1, reg2 Format V CY OV S Z Function Saturatable multiplication of signed 32-bit operands. reg1 and imm16, sign-extended to 32 bits, are multiplied together as signed integers. [If no overflow has occurred:] The result is written into reg2. [If an overflow has occurred:] The SAT bit is set. If the result is positive, the positive maximum is written into reg2; if the result is negative, the negative maximum is written into reg2. MULT3 reg1, reg2, reg3 VIII Saturatable multiplication of signed 32-bit operands. reg1 and reg2 are multiplied together as signed integers. The high-order 32 bits of the product are written into reg3. Multiplication of unsigned operands. reg1 and reg2 are multiplied together as unsigned values. The high-order 32 bits of the product (double word) are written into r30 and the low-order 32 bits are written into reg2. No operation. NOT. The NOT (ones complement) of reg1 is taken and written into reg2. OR. The OR of reg2 and reg1 is taken and written into reg2. OR. The OR of reg1 and imm16, zeroextended to a word, is taken and written into reg2. Port output. disp16, sign-extended to a word, is added to reg1 to produce an unsigned 32-bit port address. The low-order one byte of the data in reg2 is output to the resulting port address. Port output. disp16, sign-extended to a word, is added to reg1 to produce an unsigned 32-bit port address. The low-order two bytes of the data in reg2 are output to the resulting port address. Bit 0 of the unsigned 32-bit port address is masked to 0. Port output. disp16, sign-extended to a word, is added to reg1 to produce an unsigned 32-bit port address. The word of data in reg2 is output to the produced port address. Bits 0 and 1 of the unsigned 32-bit port address are masked to 0. Return from trap/interrupt handling routine. The return PC and PSW are read from the system registers so that program execution will return from the trap or interrupt handling routine. MULU reg1, reg2 I - NOP NOT reg1, reg2 III I - 0 OR reg1, reg2 I - 0 ORI imm16, reg1, reg2 V - 0 OUT.B reg2, disp16[reg1] VI - - - - OUT.H reg2, disp16[reg1] VI - - - - OUT.W reg2, disp16[reg1] VI - - - - RETI IX 37 PD705100 Instruction SAR Operand(s) reg1 ,reg2 Format I CY OV 0 S Z Function Arithmetic right shift. reg2 is arithmetically shifted to the right by the displacement specified by the low-order five bits of reg1 (MSB value is copied to the MSB in sequence). The result is written into reg2. Arithmetic right shift. reg2 is arithmetically shifted to the right by the displacement specified by imm5, zero-extended to a word. The result is written into reg2. Saturatable addition. reg1 and reg2 are added together as signed integers. [If no overflow has occurred:] The result is written into reg3. [If an overflow has occurred:] The SAT bit is set. If the result is positive, the positive maximum is written into reg3; if the result is negative, the negative maximum is written into reg3. SATSUB3 reg1, reg2, reg3 VIII Saturatable subtraction. reg1 is subtracted from reg2 as signed integers. [If no overflow has occurred:] The result is written into reg3. [If an overflow has occurred:] The SAT bit is set. If the result is positive, the positive maximum is written into reg3; if the result is negative, the negative maximum is written into reg3. SETF imm5, reg2 II Set flag condition. reg2 is set to 1 if the condition specified by the low-order four bits of imm5 matches the condition flag; otherwise it is set to 0. Logical left shift. reg2 is logically shifted to the left (0 is put on the LSB) by the displacement specified by the low-order five bits of reg1. The result is written into reg2. Logical left shift. reg2 is logically shifted to the left by the displacement specified by imm5, zero-extended to a word. The result is written into reg2. Left shift of concatenation. The 64 bits consisting of reg3 (high order) and reg2 (low order) are logically shifted to the left by the displacement specified by the low-order five bits of reg1. The high-order 32 bits of the result are written into reg3. imm5, reg2 II 0 SATADD3 reg1, reg2, reg3 VIII SHL reg1, reg2 I 0 imm5, reg2 II 0 SHLD3 reg1, reg2, reg3 VIII - - - - 38 PD705100 Instruction SHR Operand(s) reg1, reg2 Format I CY OV 0 S Z Function Logical right shift. reg2 is logically shifted to the right by the displacement specified by the low-order five bits of reg1 (0 is put on the MSB). The result is written into reg2. Logical right shift. reg2 is logically shifted to the right by the displacement specified by imm5, zero-extended to a word. The result is written into reg2. Right shift of concatenation. The 64 bits consisting of reg3 (high order) and reg2 (low order) are logically shifted to the right by the displacement specified by the low-order five bits of reg1. The low-order 32 bits of the result are written into reg3. Byte store. disp16, sign-extended to a word, is added to reg1 to produce an unsigned 32-bit address. The low-order one byte of data in reg2 is stored at the resulting address. VI Halfword store. disp16, sign-extended to a word, is added to reg1 to produce an unsigned 32-bit address. The low-order two bytes of the data in reg2 are stored at the resulting address. Bit 0 of the unsigned 32-bit address is masked to 0. Word store. disp16, sign-extended to a word, is added to reg1 to produce an unsigned 32-bit address. The word of data in reg2 is stored at the resulting address. Bits 0 and 1 of the unsigned 32-bit address are masked to 0. Processor stop. The processor is placed in stop mode. System register store. The contents of the system register identified by the system register number (regID) are set in reg2. Subtraction. reg1 is subtracted from reg2. The difference is written into reg2. Software trap. The return PC and PSW are saved in the system registers: PSW.EP = 1 Save in FEPC, FEPSW PSW.EP = 0 Save in EIPC, EIPSW The exception code is set in the ECR: PSW.EP = 1 Set in FECC PSW.EP = 0 Set in EICC PSW flags are set: PSW.EP = 1 Set NP and ID PSW.EP = 0 Set EP and ID Program execution jumps to the trap handler address corresponding to the trap vector (0-31) specified by vector and begins exception handling. imm5, reg2 II 0 SHRD3 reg1, reg2, reg3 VIII - - - - ST.B reg2, disp16[reg1] VI - - - - ST.H reg2, disp16[reg1] ST.W reg2, disp16[reg1] VI - - - - STBY IX - - - - STSR regID,reg2 II - - - - SUB reg1,reg2 I TRAP vector II - - - - 39 PD705100 Instruction XOR Operand(s) reg1,reg2 Format I CY OV 0 S Z Function Exclusive OR. The exclusive OR of reg2 and reg1 is taken and written into reg2. Exclusive OR. The exclusive OR of reg1 and imm16, zero-extended to a word, is taken and written into reg2. XORI imm16, reg1,reg2 V - 0 40 PD705100 12. INTERRUPTS AND EXCEPTIONS Interrupts are events which occur independently of program execution. They are classified into maskable and nonmaskable interrupts. In contrast, exceptions are events which are directly related to program execution. Interrupts and exceptions do not differ greatly in their control flow, but interrupts are assigned higher handling priorities than exceptions. Fatal exceptions, however, are assigned higher priorities than interrupts. Under the V830 architecture, the following interrupts and exceptions may occur. When an exception, maskable interrupt, or nonmaskable interrupt occurs, control is passed to a handler at an address which is predetermined a given cause. The cause of an exception can be identified by means of the exception code stored in the ECR (Exception Cause Register). The pertinent handler analyzes the contents of the ECR so that it can handle the exception or interrupt appropriately. Table 12-1. Exception/Interrupt Source Codes Exception/interrupt Category Exception code ECR Note 1 FFF0H FFD0H Note 2 FFBnH FFAnH FF90H FF80H FEn0H Handler address Note1 FFFFFFF0H FFFFFFE0H FFFFFFD0H FFFFFFD0H FFFFFFB0H FFFFFFA0H FFFFFF90H FFFFFF80H FFFFFEn0H FE0000n0H Return PC Reset Fatal exception NMI Double exception TRAP instruction (parameter 0x1n) TRAP instruction (parameter 0x0n) Invalid operation code Division by zero Interrupt level n (n = 0-15) HWCC.IHA = 0 HWCC.IHA = 1 Interrupt Exception Interrupt Exception Exception Exception Exception Exception Interrupt Indefinite current PC next PC current PC next PC next PC current PC current PC next PC Notes 1. Level n is represented by a hexadecimal number (n = 0-F). 2. Exception code of the exception which caused the double exception 41 PD705100 13. ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS (TA = 25C) Parameter Power supply voltage Input voltage Clock input voltage Output voltage Operating ambient temperature Storage temperature Symbol VDD VI VK VO VA Tstg VDD = 3.0 to 3.6 V VDD = 3.0 to 3.6 V Conditions Rating -0.5 to +4.5 -0.5 to +5.5 -0.5 to VDD + 0.3 -0.5 to +5.5 -10 to +85 -65 to +150 Unit V V V V C C Cautions 1. Do not connect an output (or input/output) pin of an IC device directly to any other output (or input/output) pin of the same device, with the exception of the open-drain and open-collector pins. Also, do not connect the VDD or VCC pin of an IC device directly to its GND pin or a ground. Note, however, that these restrictions do not apply to the high-impedance pins of an external circuit, whose timing has been specifically designed to avoid output collision. 2. Absolute maximum ratings are rated values, beyond which physical damage may be caused to the product; if the rated value of any of the parameters in the above table is exceeded even momentarily, the quality of the product may deteriorate. Always use the product within its rated values, therefore. For IC products, normal operation and quality are guaranteed only when the ratings and conditions described under the DC and AC characteristics are satisfied. DC CHARACTERISTICS (TA = -10 to +85C, VDD = 3.0 to 3.6 V) Parameter Low-level clock input voltage High-level clock input voltage Low-level input voltage High-level input voltage Low-level output voltage High-level output voltage Low-level input leakage current High-level input leakage current Symbol VKL VKH VIL VIH VOL VOH ILIL ILIH IOL = 3.2 mA IOH = -400 A VI = 0 V VI = VDD VI = 5.5 V Low-level output leakage current High-level output leakage current Supply currentNote ILOL ILOH IDD VO = 0 V VO = VDD During operation During HALT mode During STOP mode 120 12 30 0.85VDD -5 5 25 -5 5 170 18 150 Conditions MIN. -0.5 0.8VDD -0.5 2.0 TYP. MAX. +0.2VDD VDD + 0.3 +0.6 5.5 0.4 Unit V V V V V V A A A A A mA mA A Note The supply current (TYP.) is as measured at 3.3 V with the output pin open. The supply current (MAX.) is as measured at 3.6 V with the output pin open. Remark f is the input frequency to the BCLK pin. CAPACITANCE (TA = -10 to +85C, VDD = 3.0 to 3.6 V) Parameter Input capacitance I/O capacitance Symbol CI CIO fC = 1 MHz Conditions MIN. MAX. 15 15 Unit pF pF 42 PD705100 AC CHARACTERISTICS (TA = -10 to +85C, VDD = 3.0 to 3.6 V) AC test input waveform (except BCLK) VDD 2.0 V 0.5VDD 0V 4 ns Test point 0.6 V 0.6 V 2.0 V AC test input waveform (BCLK) VDD 0.8VDD 0.5VDD 0V 4 ns Test points 0.2VDD 0.2VDD 0.8VDD AC test output waveform (except BCLK) 0.85VDD 0.5VDD Test points 0.4 V Test load V830 output pin CL = 50 pF 43 PD705100 (1) Clock timing (a) When the internal operating frequency is 75 to 100 MHz Parameter Symbol Conditions When = 3f MIN. Clock period Clock pulse high level width Clock pulse low level width Clock pulse rise time Clock pulse fall time 1 2 When = 2f MIN. 20 3 3 MAX. 26.7 Unit MAX. 40 tCYK tKKH tKKL tKR tKF 30 3 3 ns ns ns 3 4 5 6 6 5 5 ns ns (b) When the internal operating frequency is 48 to 100 MHz Parameter Symbol Conditions When = 3f MIN. Clock period Clock pulse high level width Clock pulse low level width Clock pulse rise time Clock pulse fall time 1 2 When = 2f MIN. 20 3 3 MAX. 41.6 Unit MAX. 62.5 tCYK tKKH tKKL tKR tKF 30 3 3 ns ns ns 3 4 5 6 6 5 5 ns ns 1 2 5 4 BCLK (input) 3 Cautions 1. For clock input timings during a reset, see (2), "Reset timing." 2. The BCLK input must settle within 0.1% of tCYK ( 3. The operation is not guaranteed if tKR ( 4 1 ). 5 ) or tKF ( ) exceeds the maximum value. 44 PD705100 (2) Reset timing (a) When the internal operating frequency is 75 to 100 MHz Parameter Symbol Conditions When = 3f MIN. RESET hold time (relative to VDD VALID) Clock period (when reset) Clock high level width (when reset) Clock low level width (when reset) RESET set time (relative to BCLK, active) RESET set time (relative to BCLK, inactive) RESET hold time (relative to BCLK) RESET pulse low level width 12 13 11 When = 2f MIN. 0 MAX. 2 Unit MAX. 2 6 tHVR 0 s 7 8 tCYKR tKKHR tKKLR tSRKF 30 8 8 10 40 20 5 5 8 26.7 ns ns ns ns 9 10 tSRKR 10 8 ns tHKR tWRL Note 1 Note 2 0 10 20 0 10 20 ns ms tCYKR Notes 1. At power-on or return from stop mode 2. Other than the conditions stated in Note 1. Remarks 1. The reset signal need not satisfy tSRKF ( 2. tWRL ( 13 10 ) or tSRKR ( 11 ), provided it is within tHVR ( 6 ). ) is the number of clock cycles (tCYKR) counted after the BCLK signal has settled. (b) When the internal operating frequency is 48 to 100 MHz Parameter Symbol Conditions When = 3f MIN. RESET hold time (relative to VDD VALID) Clock period (when reset) Clock high level width (when reset) Clock low level width (when reset) RESET set time (relative to BCLK, active) RESET set time (relative to BCLK, inactive) RESET hold time (relative to BCLK) RESET pulse low level width 12 13 When = 2f MIN. 0 MAX. 2 Unit MAX. 2 6 tHVR 0 s 7 8 tCYKR tKKHR tKKLR tSRKF 30 8 8 10 62.5 20 5 5 8 41.6 ns ns ns ns 9 10 11 tSRKR 10 8 ns tHKR tWRL Note 1 Note 2 0 10 20 0 10 20 ns ms tCYKR Notes 1. At power-on or return from stop mode 2. Other than the conditions stated in Note 1. Remarks 1. The reset signal need not satisfy tSRKF ( 2. tWRL ( 10 ) or tSRKR ( 11 ), provided it is within tHVR ( 6 ). 13 ) is the number of clock cycles (tCYKR) counted after the BCLK signal has settled. 45 PD705100 0.9VDD 6 8 7 VDD BCLK (input) 10 12 11 9 RESET (input) 13 46 PD705100 (3) Memory and I/O access timing (single transfer) (1/2) (a) When the internal operating frequency is 75 to 100 MHz Parameter Symbol Conditions When = 3f MIN. Address output delay (relative to BCLK) Address output hold time (relative to BCLK) CSn output delay (relative to BCLK) 16 CSn output hold time (relative to BCLK) BCYST output delay (relative to BCLK) BCYST output hold time (relative to BCLK) READY set time (relative to BCLK) READY hold time (relative to BCLK) Data set time (relative to BCLK) Data hold time (relative to BCLK) Data output delay (from active, relative to BCLK) Data output hold time (to active, relative to BCLK) Data output delay (from float, relative to BCLK) Data output hold time (to float, relative to BCLK) 27 26 25 20 19 18 17 15 14 When = 2f MIN. 2 MAX. 13 Unit MAX. 13 tDKA 2 ns tHKA 2 13 2 13 ns tDKCS tHKCS 2 2 13 13 2 2 13 13 ns ns tDKBC 2 13 2 13 ns tHKBC 2 13 2 13 ns tSRYK tHKRY tSDK tHKD tDKDT 10 0 6 2 2 13 9 0 6 1 2 13 ns ns ns ns ns 21 22 23 24 tHKDT 2 13 2 13 ns tLZKDT 2 13 2 13 ns tHZKDT 3 20 3 20 ns 47 PD705100 (b) When the internal operating frequency is 48 to 100 MHz Parameter Symbol Conditions When = 3f MIN. Address output delay (relative to BCLK) Address output hold time (relative to BCLK) CSn output delay (relative to BCLK) 16 CSn output hold time (relative to BCLK) BCYST output delay (relative to BCLK) BCYST output hold time (relative to BCLK) READY set time (relative to BCLK) READY hold time (relative to BCLK) Data set time (relative to BCLK) Data hold time (relative to BCLK) Data output delay (from active, relative to BCLK) Data output hold time (to active, relative to BCLK) Data output delay (from float, relative to BCLK) Data output hold time (to float, relative to BCLK) 27 26 25 20 19 18 15 14 When = 2f MIN. 1 MAX. 13 Unit MAX. 13 tDKA 1 ns tHKA 1 13 1 13 ns tDKCS tHKCS 1 1 13 13 1 1 13 13 ns ns 17 tDKBC 1 13 1 13 ns tHKBC 1 13 1 13 ns tSRYK tHKRY tSDK tHKD tDKDT 10 0 7 2 1 13 10 0 7 1 1 13 ns ns ns ns ns 21 22 23 24 tHKDT 1 13 1 13 ns tLZKDT 1 13 1 13 ns tHZKDT 3 20 3 20 ns 48 PD705100 (3) Memory and I/O access timing (single transfer) (2/2) Ta BCLK (input) Ts Ts Ti 14 15 Note 1 14 15 ST0-ST3 (output) 16 17 16 CS0-CS3 (output)Note 2 18 19 BCYST (output) 20 21 20 21 READY (input) 22 23 D0-D31 (input/output) (read) 26 27 D0-D31 (input/output) (write) 24 25 D0-D31 (input/output) (write) Notes 1. A2-A27 (output), BE0-BE3 (output), R/W (output) 2. A28-A31 are output at CS0-CS3 when the chip select function is not used. Remark Dotted lines indicate the high-impedance state. 49 PD705100 (4) Memory access timing (burst transfer) (1/3) (a) When the internal operating frequency is 75 to 100 MHz Parameter Symbol Conditions When = 3f MIN. Address output delay (relative to BCLK) Address output hold time (relative to BCLK) CSn output delay (relative to BCLK) 16 CSn output hold time (relative to BCLK) BCYST output delay (relative to BCLK) BCYST output hold time (relative to BCLK) READY set time (relative to BCLK) READY hold time (relative to BCLK) Data set time (relative to BCLK) Data hold time (relative to BCLK) Data output delay (from active, relative to BCLK) Data output hold time (to active, relative to BCLK) Data output delay (from float, relative to BCLK) Data output hold time (to float, relative to BCLK) 27 26 25 20 19 18 17 15 14 When = 2f MIN. 2 MAX. 13 Unit MAX. 13 tDKA 2 ns tHKA 2 13 2 13 ns tDKCS tHKCS 2 2 13 13 2 2 13 13 ns ns tDKBC 2 13 2 13 ns tHKBC 2 13 2 13 ns tSRYK tHKRY tSDK tHKD tDKDT 10 0 6 2 2 13 9 0 6 1 2 13 ns ns ns ns ns 21 22 23 24 tHKDT 2 13 2 13 ns tLZKDT 2 13 2 13 ns tHZKDT 3 20 3 20 ns 50 PD705100 (b) When the internal operating frequency is 48 to 100 MHz Parameter Symbol Conditions When = 3f MIN. Address output delay (relative to BCLK) Address output hold time (relative to BCLK) CSn output delay (relative to BCLK) 16 CSn output hold time (relative to BCLK) BCYST output delay (relative to BCLK) BCYST output hold time (relative to BCLK) READY set time (relative to BCLK) READY hold time (relative to BCLK) Data set time (relative to BCLK) Data hold time (relative to BCLK) Data output delay (from active, relative to BCLK) Data output hold time (to active, relative to BCLK) Data output delay (from float, relative to BCLK) Data output hold time (to float, relative to BCLK) 27 26 25 20 19 18 15 14 When = 2f MIN. 1 MAX. 13 Unit MAX. 13 tDKA 1 ns tHKA 1 13 1 13 ns tDKCS tHKCS 1 1 13 13 1 1 13 13 ns ns 17 tDKBC 1 13 1 13 ns tHKBC 1 13 1 13 ns tSRYK tHKRY tSDK tHKD tDKDT 10 0 7 2 1 13 10 0 7 1 1 13 ns ns ns ns ns 21 22 23 24 tHKDT 1 13 1 13 ns tLZKDT 1 13 1 13 ns tHZKDT 3 20 3 20 ns 51 PD705100 (4) Memory access timing (burst transfer) (2/3) (c) 32-bit bus mode Ta BCLK (input) Tb1 Tb1 Tb2 Tb2 Tb3 Tb3 Tb4 Tb4 14 15 Note 1 16 17 CS0-CS3 (output)Note 2 14 15 15 A3 (output) 14 15 15 A2 (output) 18 19 BCYST (output) 20 21 20 21 READY (input) 22 23 D0-D31 (input/output) (read) 26 27 D0-D31 (input/output) (write) 24 25 D0-D31 (input/output) (write) Notes 1. A4-A27 (output), BE0-BE3 (output), ST0-ST3 (output), R/W (output) 2. A28-A31 are output at CS0-CS3 when the chip select function is not used. Remark Dotted lines indicate the high-impedance state. 52 PD705100 (4) Memory access timing (burst transfer) (3/3) (d) 16-bit bus mode Ta BCLK (input) 14 15 Tb1 Tb2 Tb3 Tb4 Tb5 Tb6 Tb7 Tb8 Ti A4-A27 (output), BE0-BE3 (output), R/W (output) 14 15 ST0-ST3 (output) 16 17 CS0-CS3 (output)Note 14 15 15 A3 (output) 14 15 15 A2 (output) 14 15 15 A1 (output) 14 15 BH (output) 18 19 BCYST (output) 20 21 READY (input) 22 23 D0-D15 (input/output) (read) Hi-Z Hi-Z 26 27 D0-D15 (input/output) (write) Hi-Z Hi-Z 24 25 D0-D15 (input/output) (write) Note A28-A31 are output at CS0-CS3 when the chip select function is not used. 53 PD705100 (5) Interrupt timing (a) When the internal operating frequency is 75 to 100 MHz Parameter Symbol Conditions When = 3f MIN. NMI set time (relative to BCLK) NMI hold time (relative to BCLK) INT set time (relative to BCLK) INT hold time (relative to BCLK) 28 29 30 When = 2f MIN. 6 1 6 1 MAX. Unit MAX. tSNK tHKN tSIK tHKI 6 2 6 2 ns ns ns ns 31 (b) When the internal operating frequency is 48 to 100 MHz Parameter Symbol Conditions When = 3f MIN. NMI set time (relative to BCLK) NMI hold time (relative to BCLK) INT set time (relative to BCLK) INT hold time (relative to BCLK) 28 29 30 When = 2f MIN. 7 1 7 1 MAX. Unit MAX. tSNK tHKN tSIK tHKI 7 2 7 2 ns ns ns ns 31 BCLK (input) 30 31 INT (input), INTV0-INTV3 (input) 28 29 NMI (input) 54 PD705100 (6) Bus hold timing (1/2) (a) When the internal operating frequency is 75 to 100 MHz Parameter Symbol Conditions When = 3f MIN. CSn output delay (relative to BCLK) CSn output hold time (relative to BCLK) READY set time (relative to BCLK) READY hold time (relative to BCLK) HLDRQ set time (relative to BCLK) 20 16 17 When = 2f MIN. 2 2 MAX. 13 13 Unit MAX. 13 13 tDKCS tHKCS 2 2 ns ns tSRYK tHKRY tSHQK tHKHQ tDKHA 10 0 6 2 2 13 9 0 6 1 2 13 ns ns ns ns ns 21 32 HLDRQ hold time (relative to BCLK) 33 HLDAK output delay (relative to BCLK) HLDAK output hold time (relative to BCLK) Address delay (from active, relative to BCLK) Address delay (from float, relative to BCLK) Data delay (from active, relative to BCLK) Data delay (from float, relative to BCLK) BCYST delay (from active, relative to BCLK) BCYST delay (from float, relative to BCLK) 41 40 34 35 tHKHA 2 13 2 13 ns 36 tHZKA 3 20 3 20 ns 37 tLZKA 2 13 2 10 ns 38 tHZKD 3 20 3 20 ns 39 tLZKD 2 13 2 10 ns tHZKBC 3 20 3 20 ns tLZKBC 2 13 2 10 ns 55 PD705100 (b) When the internal operating frequency is 48 to 100 MHz Parameter Symbol Conditions When = 3f MIN. CSn output delay (relative to BCLK) CSn output hold time (relative to BCLK) READY set time (relative to BCLK) READY hold time (relative to BCLK) HLDRQ set time (relative to BCLK) 20 16 17 When = 2f MIN. 1 1 MAX. 13 13 Unit MAX. 13 13 tDKCS tHKCS 1 1 ns ns tSRYK tHKRY tSHQK tHKHQ tDKHA 10 0 7 2 1 13 10 0 7 1 1 13 ns ns ns ns ns 21 32 HLDRQ hold time (relative to BCLK) 33 HLDAK output delay (relative to BCLK) HLDAK output hold time (relative to BCLK) Address delay (from active, relative to BCLK) Address delay (from float, relative to BCLK) Data delay (from active, relative to BCLK) Data delay (from float, relative to BCLK) BCYST delay (from active, relative to BCLK) BCYST delay (from float, relative to BCLK) 41 40 34 35 tHKHA 1 13 1 13 ns 36 tHZKA 3 20 3 20 ns 37 tLZKA 2 13 2 10 ns 38 tHZKD 3 20 3 20 ns 39 tLZKD 2 13 2 10 ns tHZKBC 3 20 3 20 ns tLZKBC 2 13 2 10 ns 56 PD705100 (6) Bus hold timing (2/2) Ta BCLK (input) Ts Ti Th Th Th Ti Ta 33 32 32 HLDRQ (input) 34 35 HLDAK (output) 36 37 Note 1 16 17 CS0-CS3 (output)Note 2 38 39 D0-D31 (input/output) (write) 40 41 BCYST (output) 20 21 READY (input) Notes 1. A2-A27 (output), BE0-BE3 (output), ST0-ST3 (output), R/W (output) 2. A28-A31 are output at CS0-CS3 when the chip select function is not used. The timings of these signals are the same as stated in Note 1. Remark Dotted lines indicate the high-impedance state. 57 PD705100 (7) Halt acknowledge cycle (1/2) (a) When the internal operating frequency is 75 to 100 MHz Parameter Symbol Conditions When = 3f MIN. Address output delay (relative to BCLK) Address output hold time (relative to BCLK) CSn output delay (relative to BCLK) CSn output hold time (relative to BCLK) BCYST output delay (relative to BCLK) BCYST output hold time (relative to BCLK) READY set time (relative to BCLK) READY hold time (relative to BCLK) Data set time (relative to BCLK) Data hold time (relative to BCLK) Data output delay (from active, relative to BCLK) Data output hold time (to active, relative to BCLK) Data output delay (from float, relative to BCLK) Data output hold time (to float, relative to BCLK) Stn output delay (relative to BCLK) Stn output hold time (relative to BCLK) 42 27 26 19 18 16 17 15 14 When = 2f MIN. 2 MAX. 13 Unit MAX. 13 tDKA 2 ns tHKA 2 13 2 13 ns tDKCS tHKCS 2 2 13 13 2 2 13 13 ns ns tDKBC 2 13 2 13 ns tHKBC 2 13 2 13 ns 20 tSRYK tHKRY tSDK tHKD tDKDT 10 0 6 2 2 13 9 0 6 1 2 13 ns ns ns ns ns 21 22 23 24 25 tHKDT 2 13 2 13 ns tLZKDT 2 13 2 13 ns tHZKDT 3 20 3 20 ns tDKST tHKST 2 2 13 13 2 2 13 13 ns ns 43 58 PD705100 (b) When the internal operating frequency is 48 to 100 MHz Parameter Symbol Conditions When = 3f MIN. Address output delay (relative to BCLK) Address output hold time (relative to BCLK) CSn output delay (relative to BCLK) CSn output hold time (relative to BCLK) BCYST output delay (relative to BCLK) BCYST output hold time (relative to BCLK) READY set time (relative to BCLK) READY hold time (relative to BCLK) Data set time (relative to BCLK) Data hold time (relative to BCLK) Data output delay (from active, relative to BCLK) Data output hold time (to active, relative to BCLK) Data output delay (from float, relative to BCLK) Data output hold time (to float, relative to BCLK) Stn output delay (relative to BCLK) Stn output hold time (relative to BCLK) 42 43 27 26 20 19 18 15 14 When = 2f MIN. 1 MAX. 10 Unit MAX. 13 tDKA 1 ns tHKA 1 13 1 10 ns 16 17 tDKCS tHKCS 1 1 13 13 1 1 10 10 ns ns tDKBC 1 13 1 13 ns tHKBC 1 13 1 13 ns tSRYK tHKRY tSDK tHKD tDKDT 10 0 7 2 1 13 10 0 7 1 1 13 ns ns ns ns ns 21 22 23 24 25 tHKDT 1 13 1 13 ns tLZKDT 1 13 1 13 ns tHZKDT 3 20 3 20 ns tDKST tHKST 1 1 13 13 1 1 13 13 ns ns 59 PD705100 (7) Halt acknowledge cycle (2/2) Ta BCLK (input) Tb Ti Ti Ti Ti Ta Tb 14 15 Note 1 16 19 BCYST (output) 16 17 CS0-CS3 (output)Note 2 42 43 ST0-ST3 (output) 20 21 Halt acknowledge READY (input) 22 23 D0-D31 (input/output) (read) 26 27 D0-D31 (input/output) (write) 24 25 D0-D31 (input/output) (write) Notes 1. A2-A27 (output), BE0-BE3 (output), R/W (output) 2. A28-A31 are output at CS0-CS3 when the chip select function is not being used. The timings of these signals are the same as stated in Note 1. Remark Dotted lines indicate the high-impedance state. 60 PD705100 14. PACKAGE DRAWING 144 PIN PLASTIC LQFP (FINE PITCH) (20 20) A B 108 109 73 72 detail of lead end C D S R Q 144 1 37 36 F G P H I M J K M N NOTE Each lead centerline is located within 0.10 mm (0.004 inch) of its true position (T.P.) at maximum material condition. L ITEM A B C D F G H I J K L M N P Q R S MILLIMETERS 22.00.2 20.00.2 20.00.2 22.00.2 1.25 1.25 0.22 +0.05 -0.04 0.10 0.5 (T.P.) 1.00.2 0.50.2 0.145 +0.055 -0.045 0.10 1.40.1 0.1250.075 3 +7 -3 1.7 MAX. INCHES 0.8660.008 0.787 +0.009 -0.008 0.787 +0.009 -0.008 0.8660.008 0.049 0.049 0.0090.002 0.004 0.020 (T.P.) 0.039 +0.009 -0.008 0.020 +0.008 -0.009 0.0060.002 0.004 0.0550.004 0.0050.003 3 +7 -3 0.067 MAX. S144GJ-50-8EU-2 61 PD705100 15. RECOMMENDED SOLDERING CONDITIONS The conditions listed below shall be met when soldering the PD705100. For details of the recommended soldering conditions, refer to our document Semiconductor Device Mounting Technology Manual (C10535E). Please consult with our sales offices in case any other soldering process is used, or in case soldering is done under different conditions. Table 15-1. Soldering Conditions for Surface-Mount Devices Soldering process Infrared ray reflow Soldering conditions Peak package's surface temperature: 235 C Reflow time: 30 seconds or less (210 C or more) Maximum allowable number of reflow processes: 2 Exposure limit: 3 daysNote (10 hours of pre-baking is required at 125 C afterward) VPS VP15-103-2 Note Maximum number of days during which the product can be stored at a temperature of 25 C and a relative humidity of 65 % or less after dry-pack package is opened. Caution Do not apply two or more different soldering methods to one chip (except for partial heating method for terminal sections). 62 PD705100 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS device behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. 63 PD705100 Regional Information Some information contained in this document may vary from country to country. Before using any NEC product in your application, please contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: * Device availability * Ordering information * Product release schedule * Availability of related technical literature * Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) * Network requirements In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. NEC Electronics Inc. (U.S.) Santa Clara, California Tel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288 NEC Electronics (Germany) GmbH Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580 NEC Electronics Hong Kong Ltd. Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044 NEC Electronics Hong Kong Ltd. NEC Electronics (France) S.A. Velizy-Villacoublay, France Tel: 01-30-67 58 00 Fax: 01-30-67 58 99 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411 NEC Electronics (Germany) GmbH Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490 NEC Electronics (France) S.A. NEC Electronics (UK) Ltd. Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290 Spain Office Madrid, Spain Tel: 01-504-2787 Fax: 01-504-2860 NEC Electronics Singapore Pte. Ltd. United Square, Singapore 1130 Tel: 253-8311 Fax: 250-3583 NEC Electronics Taiwan Ltd. NEC Electronics Italiana s.r.1. Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99 NEC Electronics (Germany) GmbH Scandinavia Office Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388 Taipei, Taiwan Tel: 02-719-2377 Fax: 02-719-5951 NEC do Brasil S.A. Cumbica-Guarulhos-SP, Brasil Tel: 011-6465-6810 Fax: 011-6465-6829 J97. 8 64 PD705100 [MEMO] 65 PD705100 Reference: Electrical Characteristics for Microcomputer (IEI-601) Note that "preliminary" is not indicated in this document, even though the related documents may be preliminary versions. V800 series, V830, and V830 family are trademarks of NEC Corporation. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. Anti-radioactive design is not implemented in this product. M4 96. 5 |
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